This invention relates to communication circuitry, and more particularly to circuitry for handling communication of digital information to which bits are added periodically for synchronization or the like.
A communication protocol that is increasingly of interest is known as “64b/66b encoding.” This is a protocol in which 64 bits of data are scrambled (e.g., to achieve balance between the number of binary ones and the numbers of binary zeros that need to be transmitted so that there is no net DC in the transmission) and two additional bits having a particular sequence are transmitted with each 64 bits as synchronization information. Thus for every 64 bits of information that need to be sent, 64 information bits and two SYNC bits are transmitted. The SYNC bits may be the sequence “10”. Extra bits of this kind may sometimes be referred to herein as “padding.”
Serial communication of padded information can be a challenge because of possibly complicated clocking issues. For example, 66 bits of information may need to be transmitted in the time in which the data source produces 64 bits of real data. Similarly, the receiver circuitry needs to receive 66 bits in the time in which it will subsequently pass on the 64 bits of real data in that 66-bit transmission.